When a load is suddenly applied to a semiconductor integrated circuit (hereinafter, referred to as LSI), a voltage drop occurs due to a parasitic resistance and a parasitic inductance present in wirings between a power supply and the LSI. At the time, the voltage drop is more increased as the parasitic resistance and the parasitic inductance are larger and a load current variation time is shorter. In recent years, the operation frequency of an LSI is as large as a few-hundred MHz or the order of a GHz, and a clock rising time is thereby significantly shortened. Therefore, the voltage drop is increasingly larger, which often causes the malfunctioning of the LSI (for example, see the Patent Document 1).
In order to lessen the voltage drop, it is effective to provide capacitors in parallel between a power supply line and a ground line of the LSI. The capacitors thus provided are generally called decoupling capacitors or bypass capacitors.
In order to control the voltage drop of the LSI, the decoupling capacitors are preferably provided as close to the LSI as possible because a wiring length is increased when the capacitors are distant from the LSI, and an L component (inductance component) is increased, which unfavorably causes a delay. A structure often adopted to deal with the disadvantage is to provide decoupling capacitors 13 in close vicinity of a semiconductor chip (LSI) 12 mounted on a printed substrate 11 as illustrated in FIG. 1.    Patent Document 1: 2002-33453 of the Japanese Patent Applications Laid-Open